Small World Communications MAP 04 T Very High Speed MAP Decoder

MAP04T Features 16 state soft–in–soft–out (SISO) maximum a posteriori (MAP) triple interleaved error control decoder and systematic recursive convolutional encoder Up to 95 Mbit/s decoding speed Rate 1/2, 1/3, or 1/4 with optional punctured inputs 6–bit received data, 8–bit soft–in and soft–out data for information and parity bits for all rates 8–bit branch metric inputs for rate 1/2 Optional code polynomials Optional block decoding with or without tail Optional max–log–MAP or log–MAP algorithm with 9 or 17 programmable SNR's Continuous sliding block algorithm with sliding block lengths of 32 or 64 Low decoding delay (400 or 784 CLK cycles) No external RAM required Asynchronous logic free design Ideal for iterative decoding of CCSDS turbo codes Available as BIT/MCS files for download into Xi-linx Virtex field programmable gate arrays (FPGA) or EDIF/VHDL core